    IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
INCLUDED_CYFITTERRV_INC EQU 1
    GET cydevicerv_trm.inc

; LED
LED__0__DR EQU CYREG_GPIO_PRT0_DR
LED__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__0__HSIOM_MASK EQU 0x0000000F
LED__0__HSIOM_SHIFT EQU 0
LED__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__0__INTR EQU CYREG_GPIO_PRT0_INTR
LED__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__0__MASK EQU 0x01
LED__0__PC EQU CYREG_GPIO_PRT0_PC
LED__0__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__0__PORT EQU 0
LED__0__PS EQU CYREG_GPIO_PRT0_PS
LED__0__SHIFT EQU 0
LED__1__DR EQU CYREG_GPIO_PRT0_DR
LED__1__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__1__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__1__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__1__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__1__HSIOM_MASK EQU 0x000000F0
LED__1__HSIOM_SHIFT EQU 4
LED__1__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__1__INTR EQU CYREG_GPIO_PRT0_INTR
LED__1__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__1__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__1__MASK EQU 0x02
LED__1__PC EQU CYREG_GPIO_PRT0_PC
LED__1__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__1__PORT EQU 0
LED__1__PS EQU CYREG_GPIO_PRT0_PS
LED__1__SHIFT EQU 1
LED__2__DR EQU CYREG_GPIO_PRT0_DR
LED__2__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__2__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__2__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__2__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__2__HSIOM_MASK EQU 0x00000F00
LED__2__HSIOM_SHIFT EQU 8
LED__2__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__2__INTR EQU CYREG_GPIO_PRT0_INTR
LED__2__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__2__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__2__MASK EQU 0x04
LED__2__PC EQU CYREG_GPIO_PRT0_PC
LED__2__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__2__PORT EQU 0
LED__2__PS EQU CYREG_GPIO_PRT0_PS
LED__2__SHIFT EQU 2
LED__3__DR EQU CYREG_GPIO_PRT0_DR
LED__3__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__3__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__3__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__3__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__3__HSIOM_MASK EQU 0x0000F000
LED__3__HSIOM_SHIFT EQU 12
LED__3__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__3__INTR EQU CYREG_GPIO_PRT0_INTR
LED__3__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__3__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__3__MASK EQU 0x08
LED__3__PC EQU CYREG_GPIO_PRT0_PC
LED__3__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__3__PORT EQU 0
LED__3__PS EQU CYREG_GPIO_PRT0_PS
LED__3__SHIFT EQU 3
LED__4__DR EQU CYREG_GPIO_PRT0_DR
LED__4__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__4__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__4__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__4__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__4__HSIOM_MASK EQU 0x000F0000
LED__4__HSIOM_SHIFT EQU 16
LED__4__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__4__INTR EQU CYREG_GPIO_PRT0_INTR
LED__4__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__4__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__4__MASK EQU 0x10
LED__4__PC EQU CYREG_GPIO_PRT0_PC
LED__4__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__4__PORT EQU 0
LED__4__PS EQU CYREG_GPIO_PRT0_PS
LED__4__SHIFT EQU 4
LED__5__DR EQU CYREG_GPIO_PRT0_DR
LED__5__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__5__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__5__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__5__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__5__HSIOM_MASK EQU 0x00F00000
LED__5__HSIOM_SHIFT EQU 20
LED__5__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__5__INTR EQU CYREG_GPIO_PRT0_INTR
LED__5__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__5__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__5__MASK EQU 0x20
LED__5__PC EQU CYREG_GPIO_PRT0_PC
LED__5__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__5__PORT EQU 0
LED__5__PS EQU CYREG_GPIO_PRT0_PS
LED__5__SHIFT EQU 5
LED__6__DR EQU CYREG_GPIO_PRT0_DR
LED__6__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__6__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__6__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__6__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__6__HSIOM_MASK EQU 0x0F000000
LED__6__HSIOM_SHIFT EQU 24
LED__6__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__6__INTR EQU CYREG_GPIO_PRT0_INTR
LED__6__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__6__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__6__MASK EQU 0x40
LED__6__PC EQU CYREG_GPIO_PRT0_PC
LED__6__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__6__PORT EQU 0
LED__6__PS EQU CYREG_GPIO_PRT0_PS
LED__6__SHIFT EQU 6
LED__7__DR EQU CYREG_GPIO_PRT0_DR
LED__7__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__7__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__7__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__7__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED__7__HSIOM_MASK EQU 0xF0000000
LED__7__HSIOM_SHIFT EQU 28
LED__7__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__7__INTR EQU CYREG_GPIO_PRT0_INTR
LED__7__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__7__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__7__MASK EQU 0x80
LED__7__PC EQU CYREG_GPIO_PRT0_PC
LED__7__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__7__PORT EQU 0
LED__7__PS EQU CYREG_GPIO_PRT0_PS
LED__7__SHIFT EQU 7
LED__DR EQU CYREG_GPIO_PRT0_DR
LED__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
LED__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
LED__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
LED__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__INTR EQU CYREG_GPIO_PRT0_INTR
LED__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
LED__INTSTAT EQU CYREG_GPIO_PRT0_INTR
LED__MASK EQU 0xFF
LED__PC EQU CYREG_GPIO_PRT0_PC
LED__PC2 EQU CYREG_GPIO_PRT0_PC2
LED__PORT EQU 0
LED__PS EQU CYREG_GPIO_PRT0_PS
LED__SHIFT EQU 0

; UART_rx
UART_rx__0__DR EQU CYREG_GPIO_PRT1_DR
UART_rx__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_rx__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_rx__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_rx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
UART_rx__0__HSIOM_GPIO EQU 0
UART_rx__0__HSIOM_I2C EQU 14
UART_rx__0__HSIOM_I2C_SCL EQU 14
UART_rx__0__HSIOM_MASK EQU 0x0000000F
UART_rx__0__HSIOM_SHIFT EQU 0
UART_rx__0__HSIOM_SPI EQU 15
UART_rx__0__HSIOM_SPI_MOSI EQU 15
UART_rx__0__HSIOM_UART EQU 9
UART_rx__0__HSIOM_UART_RX EQU 9
UART_rx__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__0__INTR EQU CYREG_GPIO_PRT1_INTR
UART_rx__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_rx__0__MASK EQU 0x01
UART_rx__0__PC EQU CYREG_GPIO_PRT1_PC
UART_rx__0__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_rx__0__PORT EQU 1
UART_rx__0__PS EQU CYREG_GPIO_PRT1_PS
UART_rx__0__SHIFT EQU 0
UART_rx__DR EQU CYREG_GPIO_PRT1_DR
UART_rx__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_rx__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_rx__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_rx__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__INTR EQU CYREG_GPIO_PRT1_INTR
UART_rx__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_rx__MASK EQU 0x01
UART_rx__PC EQU CYREG_GPIO_PRT1_PC
UART_rx__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_rx__PORT EQU 1
UART_rx__PS EQU CYREG_GPIO_PRT1_PS
UART_rx__SHIFT EQU 0

; UART_SCB
UART_SCB__CTRL EQU CYREG_SCB0_CTRL
UART_SCB__EZ_DATA0 EQU CYREG_SCB0_EZ_DATA0
UART_SCB__EZ_DATA1 EQU CYREG_SCB0_EZ_DATA1
UART_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10
UART_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11
UART_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12
UART_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13
UART_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14
UART_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15
UART_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16
UART_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17
UART_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18
UART_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19
UART_SCB__EZ_DATA2 EQU CYREG_SCB0_EZ_DATA2
UART_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20
UART_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21
UART_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22
UART_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23
UART_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24
UART_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25
UART_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26
UART_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27
UART_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28
UART_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29
UART_SCB__EZ_DATA3 EQU CYREG_SCB0_EZ_DATA3
UART_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30
UART_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31
UART_SCB__EZ_DATA4 EQU CYREG_SCB0_EZ_DATA4
UART_SCB__EZ_DATA5 EQU CYREG_SCB0_EZ_DATA5
UART_SCB__EZ_DATA6 EQU CYREG_SCB0_EZ_DATA6
UART_SCB__EZ_DATA7 EQU CYREG_SCB0_EZ_DATA7
UART_SCB__EZ_DATA8 EQU CYREG_SCB0_EZ_DATA8
UART_SCB__EZ_DATA9 EQU CYREG_SCB0_EZ_DATA9
UART_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG
UART_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL
UART_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD
UART_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD
UART_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS
UART_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE
UART_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC
UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK
UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED
UART_SCB__INTR_M EQU CYREG_SCB0_INTR_M
UART_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK
UART_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED
UART_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET
UART_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX
UART_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK
UART_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED
UART_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET
UART_SCB__INTR_S EQU CYREG_SCB0_INTR_S
UART_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK
UART_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED
UART_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET
UART_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC
UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK
UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED
UART_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX
UART_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK
UART_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED
UART_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET
UART_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL
UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL
UART_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD
UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT
UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS
UART_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH
UART_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL
UART_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS
UART_SCB__SS0_POSISTION EQU 0
UART_SCB__SS1_POSISTION EQU 1
UART_SCB__SS2_POSISTION EQU 2
UART_SCB__SS3_POSISTION EQU 3
UART_SCB__STATUS EQU CYREG_SCB0_STATUS
UART_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL
UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL
UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS
UART_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR
UART_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL
UART_SCB__UART_FLOW_CTRL EQU CYREG_SCB0_UART_FLOW_CTRL
UART_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL
UART_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS
UART_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL

; UART_SCB_IRQ
UART_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
UART_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
UART_SCB_IRQ__INTC_MASK EQU 0x80
UART_SCB_IRQ__INTC_NUMBER EQU 7
UART_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0000000
UART_SCB_IRQ__INTC_PRIOR_NUM EQU 2
UART_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR1
UART_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
UART_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

; UART_SCBCLK
UART_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL0
UART_SCBCLK__DIV_ID EQU 0x00000080
UART_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_5_CTL0
UART_SCBCLK__FRAC_MASK EQU 0x000000F8
UART_SCBCLK__PA_DIV_ID EQU 0x000000FF

; UART_tx
UART_tx__0__DR EQU CYREG_GPIO_PRT1_DR
UART_tx__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_tx__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_tx__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
UART_tx__0__HSIOM_GPIO EQU 0
UART_tx__0__HSIOM_I2C EQU 14
UART_tx__0__HSIOM_I2C_SDA EQU 14
UART_tx__0__HSIOM_MASK EQU 0x000000F0
UART_tx__0__HSIOM_SHIFT EQU 4
UART_tx__0__HSIOM_SPI EQU 15
UART_tx__0__HSIOM_SPI_MISO EQU 15
UART_tx__0__HSIOM_UART EQU 9
UART_tx__0__HSIOM_UART_TX EQU 9
UART_tx__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__0__INTR EQU CYREG_GPIO_PRT1_INTR
UART_tx__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_tx__0__MASK EQU 0x02
UART_tx__0__PC EQU CYREG_GPIO_PRT1_PC
UART_tx__0__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_tx__0__PORT EQU 1
UART_tx__0__PS EQU CYREG_GPIO_PRT1_PS
UART_tx__0__SHIFT EQU 1
UART_tx__DR EQU CYREG_GPIO_PRT1_DR
UART_tx__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_tx__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_tx__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_tx__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__INTR EQU CYREG_GPIO_PRT1_INTR
UART_tx__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_tx__MASK EQU 0x02
UART_tx__PC EQU CYREG_GPIO_PRT1_PC
UART_tx__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_tx__PORT EQU 1
UART_tx__PS EQU CYREG_GPIO_PRT1_PS
UART_tx__SHIFT EQU 1

; Clock_2
Clock_2__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL6
Clock_2__DIV_ID EQU 0x00000044
Clock_2__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL4
Clock_2__PA_DIV_ID EQU 0x000000FF

; CapSense_AdcInput
CapSense_AdcInput__0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_AdcInput__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_AdcInput__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_AdcInput__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_AdcInput__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
CapSense_AdcInput__0__HSIOM_MASK EQU 0x00F00000
CapSense_AdcInput__0__HSIOM_SHIFT EQU 20
CapSense_AdcInput__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_AdcInput__0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_AdcInput__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_AdcInput__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_AdcInput__0__MASK EQU 0x20
CapSense_AdcInput__0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_AdcInput__0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_AdcInput__0__PORT EQU 2
CapSense_AdcInput__0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_AdcInput__0__SHIFT EQU 5
CapSense_AdcInput__1__DR EQU CYREG_GPIO_PRT3_DR
CapSense_AdcInput__1__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_AdcInput__1__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_AdcInput__1__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_AdcInput__1__HSIOM EQU CYREG_HSIOM_PORT_SEL3
CapSense_AdcInput__1__HSIOM_MASK EQU 0x00F00000
CapSense_AdcInput__1__HSIOM_SHIFT EQU 20
CapSense_AdcInput__1__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_AdcInput__1__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_AdcInput__1__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_AdcInput__1__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_AdcInput__1__MASK EQU 0x20
CapSense_AdcInput__1__PC EQU CYREG_GPIO_PRT3_PC
CapSense_AdcInput__1__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_AdcInput__1__PORT EQU 3
CapSense_AdcInput__1__PS EQU CYREG_GPIO_PRT3_PS
CapSense_AdcInput__1__SHIFT EQU 5
CapSense_AdcInput__Ch0__DR EQU CYREG_GPIO_PRT2_DR
CapSense_AdcInput__Ch0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
CapSense_AdcInput__Ch0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
CapSense_AdcInput__Ch0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
CapSense_AdcInput__Ch0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_AdcInput__Ch0__INTR EQU CYREG_GPIO_PRT2_INTR
CapSense_AdcInput__Ch0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
CapSense_AdcInput__Ch0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
CapSense_AdcInput__Ch0__MASK EQU 0x20
CapSense_AdcInput__Ch0__PC EQU CYREG_GPIO_PRT2_PC
CapSense_AdcInput__Ch0__PC2 EQU CYREG_GPIO_PRT2_PC2
CapSense_AdcInput__Ch0__PORT EQU 2
CapSense_AdcInput__Ch0__PS EQU CYREG_GPIO_PRT2_PS
CapSense_AdcInput__Ch0__SHIFT EQU 5
CapSense_AdcInput__Ch1__DR EQU CYREG_GPIO_PRT3_DR
CapSense_AdcInput__Ch1__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_AdcInput__Ch1__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_AdcInput__Ch1__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_AdcInput__Ch1__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_AdcInput__Ch1__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_AdcInput__Ch1__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_AdcInput__Ch1__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_AdcInput__Ch1__MASK EQU 0x20
CapSense_AdcInput__Ch1__PC EQU CYREG_GPIO_PRT3_PC
CapSense_AdcInput__Ch1__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_AdcInput__Ch1__PORT EQU 3
CapSense_AdcInput__Ch1__PS EQU CYREG_GPIO_PRT3_PS
CapSense_AdcInput__Ch1__SHIFT EQU 5

; CapSense_Cmod
CapSense_Cmod__0__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Cmod__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Cmod__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Cmod__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Cmod__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
CapSense_Cmod__0__HSIOM_MASK EQU 0x00000F00
CapSense_Cmod__0__HSIOM_SHIFT EQU 8
CapSense_Cmod__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__0__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__0__MASK EQU 0x04
CapSense_Cmod__0__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Cmod__0__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Cmod__0__PORT EQU 4
CapSense_Cmod__0__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Cmod__0__SHIFT EQU 2
CapSense_Cmod__Cmod__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Cmod__Cmod__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Cmod__Cmod__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Cmod__Cmod__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Cmod__Cmod__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__Cmod__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__Cmod__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__Cmod__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__Cmod__MASK EQU 0x04
CapSense_Cmod__Cmod__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Cmod__Cmod__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Cmod__Cmod__PORT EQU 4
CapSense_Cmod__Cmod__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Cmod__Cmod__SHIFT EQU 2
CapSense_Cmod__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Cmod__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Cmod__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Cmod__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Cmod__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Cmod__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Cmod__MASK EQU 0x04
CapSense_Cmod__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Cmod__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Cmod__PORT EQU 4
CapSense_Cmod__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Cmod__SHIFT EQU 2

; CapSense_CSD
CapSense_CSD__ADC_CTL EQU CYREG_CSD_ADC_CTL
CapSense_CSD__CMOD_PAD EQU 1
CapSense_CSD__CSD_CONFIG EQU CYREG_CSD_CONFIG
CapSense_CSD__CSD_INTR EQU CYREG_CSD_INTR
CapSense_CSD__CSD_INTR_SET EQU CYREG_CSD_INTR_SET
CapSense_CSD__CSD_NUMBER EQU 0
CapSense_CSD__CSD_STATUS EQU CYREG_CSD_STATUS
CapSense_CSD__CSDCMP EQU CYREG_CSD_CSDCMP
CapSense_CSD__CSH_TANK_PAD EQU 2
CapSense_CSD__CSHIELD_PAD EQU 4
CapSense_CSD__DEDICATED_IO EQU CapSense_CSD__CMOD_PAD
CapSense_CSD__HSCMP EQU CYREG_CSD_HSCMP
CapSense_CSD__INTR_MASK EQU CYREG_CSD_INTR_MASK
CapSense_CSD__REFGEN EQU CYREG_CSD_REFGEN
CapSense_CSD__RESULT_VAL1 EQU CYREG_CSD_RESULT_VAL1
CapSense_CSD__RESULT_VAL2 EQU CYREG_CSD_RESULT_VAL2
CapSense_CSD__SENSE_DUTY EQU CYREG_CSD_SENSE_DUTY
CapSense_CSD__SENSE_PERIOD EQU CYREG_CSD_SENSE_PERIOD
CapSense_CSD__SEQ_INIT_CNT EQU CYREG_CSD_SEQ_INIT_CNT
CapSense_CSD__SEQ_NORM_CNT EQU CYREG_CSD_SEQ_NORM_CNT
CapSense_CSD__SEQ_START EQU CYREG_CSD_SEQ_START
CapSense_CSD__SEQ_TIME EQU CYREG_CSD_SEQ_TIME
CapSense_CSD__SW_AMUXBUF_SEL EQU CYREG_CSD_SW_AMUXBUF_SEL
CapSense_CSD__SW_BYP_SEL EQU CYREG_CSD_SW_BYP_SEL
CapSense_CSD__SW_CMP_N_SEL EQU CYREG_CSD_SW_CMP_N_SEL
CapSense_CSD__SW_CMP_P_SEL EQU CYREG_CSD_SW_CMP_P_SEL
CapSense_CSD__SW_DSI_SEL EQU CYREG_CSD_SW_DSI_SEL
CapSense_CSD__SW_FW_MOD_SEL EQU CYREG_CSD_SW_FW_MOD_SEL
CapSense_CSD__SW_FW_TANK_SEL EQU CYREG_CSD_SW_FW_TANK_SEL
CapSense_CSD__SW_HS_N_SEL EQU CYREG_CSD_SW_HS_N_SEL
CapSense_CSD__SW_HS_P_SEL EQU CYREG_CSD_SW_HS_P_SEL
CapSense_CSD__SW_REFGEN_SEL EQU CYREG_CSD_SW_REFGEN_SEL
CapSense_CSD__SW_RES EQU CYREG_CSD_SW_RES
CapSense_CSD__SW_SHIELD_SEL EQU CYREG_CSD_SW_SHIELD_SEL

; CapSense_IDACComp
CapSense_IDACComp__CONFIG EQU CYREG_CSD_CONFIG
CapSense_IDACComp__IDAC EQU CYREG_CSD_IDACB
CapSense_IDACComp__POSITION EQU 1

; CapSense_IDACMod
CapSense_IDACMod__CONFIG EQU CYREG_CSD_CONFIG
CapSense_IDACMod__IDAC EQU CYREG_CSD_IDACA
CapSense_IDACMod__POSITION EQU 0

; CapSense_ISR
CapSense_ISR__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
CapSense_ISR__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
CapSense_ISR__INTC_MASK EQU 0x400
CapSense_ISR__INTC_NUMBER EQU 10
CapSense_ISR__INTC_PRIOR_MASK EQU 0xC00000
CapSense_ISR__INTC_PRIOR_NUM EQU 0
CapSense_ISR__INTC_PRIOR_REG EQU CYREG_CM0P_IPR2
CapSense_ISR__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
CapSense_ISR__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

; CapSense_ModClk
CapSense_ModClk__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL2
CapSense_ModClk__DIV_ID EQU 0x00000040
CapSense_ModClk__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0
CapSense_ModClk__PA_DIV_ID EQU 0x000000FF

; CapSense_Shield
CapSense_Shield__0__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Shield__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Shield__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Shield__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Shield__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
CapSense_Shield__0__HSIOM_MASK EQU 0x0F000000
CapSense_Shield__0__HSIOM_SHIFT EQU 24
CapSense_Shield__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Shield__0__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Shield__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Shield__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Shield__0__MASK EQU 0x40
CapSense_Shield__0__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Shield__0__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Shield__0__PORT EQU 1
CapSense_Shield__0__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Shield__0__SHIFT EQU 6
CapSense_Shield__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Shield__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Shield__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Shield__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Shield__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Shield__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Shield__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Shield__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Shield__MASK EQU 0x40
CapSense_Shield__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Shield__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Shield__PORT EQU 1
CapSense_Shield__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Shield__Shield__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Shield__Shield__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Shield__Shield__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Shield__Shield__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Shield__Shield__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Shield__Shield__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Shield__Shield__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Shield__Shield__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Shield__Shield__MASK EQU 0x40
CapSense_Shield__Shield__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Shield__Shield__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Shield__Shield__PORT EQU 1
CapSense_Shield__Shield__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Shield__Shield__SHIFT EQU 6
CapSense_Shield__SHIFT EQU 6

; CapSense_Sns
CapSense_Sns__0__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
CapSense_Sns__0__HSIOM_MASK EQU 0x00F00000
CapSense_Sns__0__HSIOM_SHIFT EQU 20
CapSense_Sns__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__0__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__0__MASK EQU 0x20
CapSense_Sns__0__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__0__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__0__PORT EQU 1
CapSense_Sns__0__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__0__SHIFT EQU 5
CapSense_Sns__1__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__1__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__1__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__1__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__1__HSIOM EQU CYREG_HSIOM_PORT_SEL1
CapSense_Sns__1__HSIOM_MASK EQU 0x000F0000
CapSense_Sns__1__HSIOM_SHIFT EQU 16
CapSense_Sns__1__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__1__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__1__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__1__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__1__MASK EQU 0x10
CapSense_Sns__1__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__1__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__1__PORT EQU 1
CapSense_Sns__1__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__1__SHIFT EQU 4
CapSense_Sns__2__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__2__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__2__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__2__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__2__HSIOM EQU CYREG_HSIOM_PORT_SEL1
CapSense_Sns__2__HSIOM_MASK EQU 0x0000F000
CapSense_Sns__2__HSIOM_SHIFT EQU 12
CapSense_Sns__2__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__2__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__2__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__2__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__2__MASK EQU 0x08
CapSense_Sns__2__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__2__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__2__PORT EQU 1
CapSense_Sns__2__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__2__SHIFT EQU 3
CapSense_Sns__3__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__3__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__3__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__3__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__3__HSIOM EQU CYREG_HSIOM_PORT_SEL1
CapSense_Sns__3__HSIOM_MASK EQU 0x00000F00
CapSense_Sns__3__HSIOM_SHIFT EQU 8
CapSense_Sns__3__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__3__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__3__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__3__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__3__MASK EQU 0x04
CapSense_Sns__3__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__3__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__3__PORT EQU 1
CapSense_Sns__3__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__3__SHIFT EQU 2
CapSense_Sns__4__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__4__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__4__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__4__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__4__HSIOM EQU CYREG_HSIOM_PORT_SEL3
CapSense_Sns__4__HSIOM_MASK EQU 0x0F000000
CapSense_Sns__4__HSIOM_SHIFT EQU 24
CapSense_Sns__4__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__4__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__4__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__4__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__4__MASK EQU 0x40
CapSense_Sns__4__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__4__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__4__PORT EQU 3
CapSense_Sns__4__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__4__SHIFT EQU 6
CapSense_Sns__5__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__5__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__5__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__5__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__5__HSIOM EQU CYREG_HSIOM_PORT_SEL3
CapSense_Sns__5__HSIOM_MASK EQU 0xF0000000
CapSense_Sns__5__HSIOM_SHIFT EQU 28
CapSense_Sns__5__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__5__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__5__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__5__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__5__MASK EQU 0x80
CapSense_Sns__5__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__5__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__5__PORT EQU 3
CapSense_Sns__5__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__5__SHIFT EQU 7
CapSense_Sns__6__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Sns__6__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Sns__6__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Sns__6__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Sns__6__HSIOM EQU CYREG_HSIOM_PORT_SEL4
CapSense_Sns__6__HSIOM_MASK EQU 0x0000000F
CapSense_Sns__6__HSIOM_SHIFT EQU 0
CapSense_Sns__6__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Sns__6__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Sns__6__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Sns__6__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Sns__6__MASK EQU 0x01
CapSense_Sns__6__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Sns__6__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Sns__6__PORT EQU 4
CapSense_Sns__6__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Sns__6__SHIFT EQU 0
CapSense_Sns__Button0_Sns0__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__Button0_Sns0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__Button0_Sns0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__Button0_Sns0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__Button0_Sns0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button0_Sns0__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button0_Sns0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button0_Sns0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button0_Sns0__MASK EQU 0x20
CapSense_Sns__Button0_Sns0__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__Button0_Sns0__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__Button0_Sns0__PORT EQU 1
CapSense_Sns__Button0_Sns0__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__Button0_Sns0__SHIFT EQU 5
CapSense_Sns__Button1_Sns0__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__Button1_Sns0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__Button1_Sns0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__Button1_Sns0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__Button1_Sns0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button1_Sns0__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button1_Sns0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button1_Sns0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button1_Sns0__MASK EQU 0x10
CapSense_Sns__Button1_Sns0__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__Button1_Sns0__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__Button1_Sns0__PORT EQU 1
CapSense_Sns__Button1_Sns0__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__Button1_Sns0__SHIFT EQU 4
CapSense_Sns__Button2_Sns0__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__Button2_Sns0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__Button2_Sns0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__Button2_Sns0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__Button2_Sns0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button2_Sns0__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button2_Sns0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button2_Sns0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button2_Sns0__MASK EQU 0x08
CapSense_Sns__Button2_Sns0__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__Button2_Sns0__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__Button2_Sns0__PORT EQU 1
CapSense_Sns__Button2_Sns0__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__Button2_Sns0__SHIFT EQU 3
CapSense_Sns__Button3_Sns0__DR EQU CYREG_GPIO_PRT1_DR
CapSense_Sns__Button3_Sns0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
CapSense_Sns__Button3_Sns0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
CapSense_Sns__Button3_Sns0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
CapSense_Sns__Button3_Sns0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button3_Sns0__INTR EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button3_Sns0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
CapSense_Sns__Button3_Sns0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
CapSense_Sns__Button3_Sns0__MASK EQU 0x04
CapSense_Sns__Button3_Sns0__PC EQU CYREG_GPIO_PRT1_PC
CapSense_Sns__Button3_Sns0__PC2 EQU CYREG_GPIO_PRT1_PC2
CapSense_Sns__Button3_Sns0__PORT EQU 1
CapSense_Sns__Button3_Sns0__PS EQU CYREG_GPIO_PRT1_PS
CapSense_Sns__Button3_Sns0__SHIFT EQU 2
CapSense_Sns__Button4_Sns0__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__Button4_Sns0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__Button4_Sns0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__Button4_Sns0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__Button4_Sns0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__Button4_Sns0__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__Button4_Sns0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__Button4_Sns0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__Button4_Sns0__MASK EQU 0x40
CapSense_Sns__Button4_Sns0__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__Button4_Sns0__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__Button4_Sns0__PORT EQU 3
CapSense_Sns__Button4_Sns0__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__Button4_Sns0__SHIFT EQU 6
CapSense_Sns__Button5_Sns0__DR EQU CYREG_GPIO_PRT3_DR
CapSense_Sns__Button5_Sns0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
CapSense_Sns__Button5_Sns0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
CapSense_Sns__Button5_Sns0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
CapSense_Sns__Button5_Sns0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__Button5_Sns0__INTR EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__Button5_Sns0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
CapSense_Sns__Button5_Sns0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
CapSense_Sns__Button5_Sns0__MASK EQU 0x80
CapSense_Sns__Button5_Sns0__PC EQU CYREG_GPIO_PRT3_PC
CapSense_Sns__Button5_Sns0__PC2 EQU CYREG_GPIO_PRT3_PC2
CapSense_Sns__Button5_Sns0__PORT EQU 3
CapSense_Sns__Button5_Sns0__PS EQU CYREG_GPIO_PRT3_PS
CapSense_Sns__Button5_Sns0__SHIFT EQU 7
CapSense_Sns__Button6_Sns0__DR EQU CYREG_GPIO_PRT4_DR
CapSense_Sns__Button6_Sns0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
CapSense_Sns__Button6_Sns0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
CapSense_Sns__Button6_Sns0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
CapSense_Sns__Button6_Sns0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Sns__Button6_Sns0__INTR EQU CYREG_GPIO_PRT4_INTR
CapSense_Sns__Button6_Sns0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
CapSense_Sns__Button6_Sns0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
CapSense_Sns__Button6_Sns0__MASK EQU 0x01
CapSense_Sns__Button6_Sns0__PC EQU CYREG_GPIO_PRT4_PC
CapSense_Sns__Button6_Sns0__PC2 EQU CYREG_GPIO_PRT4_PC2
CapSense_Sns__Button6_Sns0__PORT EQU 4
CapSense_Sns__Button6_Sns0__PS EQU CYREG_GPIO_PRT4_PS
CapSense_Sns__Button6_Sns0__SHIFT EQU 0

; PWM_Beep_cy_m0s8_tcpwm_1
PWM_Beep_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT0_CC
PWM_Beep_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT0_CC_BUFF
PWM_Beep_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT0_COUNTER
PWM_Beep_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT0_CTRL
PWM_Beep_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT0_INTR
PWM_Beep_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT0_INTR_MASK
PWM_Beep_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT0_INTR_MASKED
PWM_Beep_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT0_INTR_SET
PWM_Beep_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT0_PERIOD
PWM_Beep_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT0_PERIOD_BUFF
PWM_Beep_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT0_STATUS
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x01
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 0
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x100
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 8
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x1000000
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 24
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x10000
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 16
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x01
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 0
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x01
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 0
PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 0
PWM_Beep_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT0_TR_CTRL0
PWM_Beep_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT0_TR_CTRL1
PWM_Beep_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT0_TR_CTRL2

; Pin_Beep
Pin_Beep__0__DR EQU CYREG_GPIO_PRT2_DR
Pin_Beep__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_Beep__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_Beep__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_Beep__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_Beep__0__HSIOM_MASK EQU 0x000F0000
Pin_Beep__0__HSIOM_SHIFT EQU 16
Pin_Beep__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Beep__0__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_Beep__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Beep__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_Beep__0__MASK EQU 0x10
Pin_Beep__0__PC EQU CYREG_GPIO_PRT2_PC
Pin_Beep__0__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_Beep__0__PORT EQU 2
Pin_Beep__0__PS EQU CYREG_GPIO_PRT2_PS
Pin_Beep__0__SHIFT EQU 4
Pin_Beep__DR EQU CYREG_GPIO_PRT2_DR
Pin_Beep__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_Beep__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_Beep__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_Beep__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Beep__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_Beep__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Beep__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_Beep__MASK EQU 0x10
Pin_Beep__PC EQU CYREG_GPIO_PRT2_PC
Pin_Beep__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_Beep__PORT EQU 2
Pin_Beep__PS EQU CYREG_GPIO_PRT2_PS
Pin_Beep__SHIFT EQU 4

; Radar_EN
Radar_EN__0__DR EQU CYREG_GPIO_PRT4_DR
Radar_EN__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
Radar_EN__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
Radar_EN__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
Radar_EN__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4
Radar_EN__0__HSIOM_MASK EQU 0x0000F000
Radar_EN__0__HSIOM_SHIFT EQU 12
Radar_EN__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
Radar_EN__0__INTR EQU CYREG_GPIO_PRT4_INTR
Radar_EN__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
Radar_EN__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR
Radar_EN__0__MASK EQU 0x08
Radar_EN__0__PC EQU CYREG_GPIO_PRT4_PC
Radar_EN__0__PC2 EQU CYREG_GPIO_PRT4_PC2
Radar_EN__0__PORT EQU 4
Radar_EN__0__PS EQU CYREG_GPIO_PRT4_PS
Radar_EN__0__SHIFT EQU 3
Radar_EN__DR EQU CYREG_GPIO_PRT4_DR
Radar_EN__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR
Radar_EN__DR_INV EQU CYREG_GPIO_PRT4_DR_INV
Radar_EN__DR_SET EQU CYREG_GPIO_PRT4_DR_SET
Radar_EN__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG
Radar_EN__INTR EQU CYREG_GPIO_PRT4_INTR
Radar_EN__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG
Radar_EN__INTSTAT EQU CYREG_GPIO_PRT4_INTR
Radar_EN__MASK EQU 0x08
Radar_EN__PC EQU CYREG_GPIO_PRT4_PC
Radar_EN__PC2 EQU CYREG_GPIO_PRT4_PC2
Radar_EN__PORT EQU 4
Radar_EN__PS EQU CYREG_GPIO_PRT4_PS
Radar_EN__SHIFT EQU 3

; Timer8_1_cy_m0s8_tcpwm_1
Timer8_1_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT3_CC
Timer8_1_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT3_CC_BUFF
Timer8_1_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT3_COUNTER
Timer8_1_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT3_CTRL
Timer8_1_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT3_INTR
Timer8_1_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT3_INTR_MASK
Timer8_1_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT3_INTR_MASKED
Timer8_1_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT3_INTR_SET
Timer8_1_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT3_PERIOD
Timer8_1_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT3_PERIOD_BUFF
Timer8_1_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT3_STATUS
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x08
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 3
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x800
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 11
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x8000000
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 27
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x80000
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 19
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x08
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 3
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x08
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 3
Timer8_1_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 3
Timer8_1_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT3_TR_CTRL0
Timer8_1_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT3_TR_CTRL1
Timer8_1_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT3_TR_CTRL2

; Timer8_1_ISR
Timer8_1_ISR__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER
Timer8_1_ISR__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR
Timer8_1_ISR__INTC_MASK EQU 0x4000
Timer8_1_ISR__INTC_NUMBER EQU 14
Timer8_1_ISR__INTC_PRIOR_MASK EQU 0xC00000
Timer8_1_ISR__INTC_PRIOR_NUM EQU 1
Timer8_1_ISR__INTC_PRIOR_REG EQU CYREG_CM0P_IPR3
Timer8_1_ISR__INTC_SET_EN_REG EQU CYREG_CM0P_ISER
Timer8_1_ISR__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR

; InputZero
InputZero__0__DR EQU CYREG_GPIO_PRT1_DR
InputZero__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
InputZero__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
InputZero__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
InputZero__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
InputZero__0__HSIOM_MASK EQU 0xF0000000
InputZero__0__HSIOM_SHIFT EQU 28
InputZero__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
InputZero__0__INTR EQU CYREG_GPIO_PRT1_INTR
InputZero__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
InputZero__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
InputZero__0__MASK EQU 0x80
InputZero__0__PC EQU CYREG_GPIO_PRT1_PC
InputZero__0__PC2 EQU CYREG_GPIO_PRT1_PC2
InputZero__0__PORT EQU 1
InputZero__0__PS EQU CYREG_GPIO_PRT1_PS
InputZero__0__SHIFT EQU 7
InputZero__DR EQU CYREG_GPIO_PRT1_DR
InputZero__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
InputZero__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
InputZero__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
InputZero__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
InputZero__INTR EQU CYREG_GPIO_PRT1_INTR
InputZero__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
InputZero__INTSTAT EQU CYREG_GPIO_PRT1_INTR
InputZero__MASK EQU 0x80
InputZero__PC EQU CYREG_GPIO_PRT1_PC
InputZero__PC2 EQU CYREG_GPIO_PRT1_PC2
InputZero__PORT EQU 1
InputZero__PS EQU CYREG_GPIO_PRT1_PS
InputZero__SHIFT EQU 7

; PWM_Local_cy_m0s8_tcpwm_1
PWM_Local_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT4_CC
PWM_Local_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT4_CC_BUFF
PWM_Local_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT4_COUNTER
PWM_Local_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT4_CTRL
PWM_Local_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT4_INTR
PWM_Local_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT4_INTR_MASK
PWM_Local_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT4_INTR_MASKED
PWM_Local_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT4_INTR_SET
PWM_Local_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT4_PERIOD
PWM_Local_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT4_PERIOD_BUFF
PWM_Local_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT4_STATUS
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x10
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 4
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x1000
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 12
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x10000000
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 28
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x100000
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 20
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x10
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 4
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x10
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 4
PWM_Local_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 4
PWM_Local_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT4_TR_CTRL0
PWM_Local_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT4_TR_CTRL1
PWM_Local_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT4_TR_CTRL2

; PWM_Night_cy_m0s8_tcpwm_1
PWM_Night_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT2_CC
PWM_Night_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT2_CC_BUFF
PWM_Night_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT2_COUNTER
PWM_Night_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT2_CTRL
PWM_Night_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT2_INTR
PWM_Night_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT2_INTR_MASK
PWM_Night_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT2_INTR_MASKED
PWM_Night_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT2_INTR_SET
PWM_Night_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT2_PERIOD
PWM_Night_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT2_PERIOD_BUFF
PWM_Night_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT2_STATUS
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x04
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 2
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x400
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 10
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x4000000
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 26
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x40000
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 18
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x04
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 2
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x04
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 2
PWM_Night_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 2
PWM_Night_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT2_TR_CTRL0
PWM_Night_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT2_TR_CTRL1
PWM_Night_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT2_TR_CTRL2

; Pin_Local
Pin_Local__0__DR EQU CYREG_GPIO_PRT2_DR
Pin_Local__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_Local__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_Local__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_Local__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_Local__0__HSIOM_MASK EQU 0x0000000F
Pin_Local__0__HSIOM_SHIFT EQU 0
Pin_Local__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Local__0__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_Local__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Local__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_Local__0__MASK EQU 0x01
Pin_Local__0__PC EQU CYREG_GPIO_PRT2_PC
Pin_Local__0__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_Local__0__PORT EQU 2
Pin_Local__0__PS EQU CYREG_GPIO_PRT2_PS
Pin_Local__0__SHIFT EQU 0
Pin_Local__DR EQU CYREG_GPIO_PRT2_DR
Pin_Local__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_Local__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_Local__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_Local__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Local__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_Local__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Local__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_Local__MASK EQU 0x01
Pin_Local__PC EQU CYREG_GPIO_PRT2_PC
Pin_Local__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_Local__PORT EQU 2
Pin_Local__PS EQU CYREG_GPIO_PRT2_PS
Pin_Local__SHIFT EQU 0

; Pin_Night
Pin_Night__0__DR EQU CYREG_GPIO_PRT3_DR
Pin_Night__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
Pin_Night__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
Pin_Night__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
Pin_Night__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
Pin_Night__0__HSIOM_MASK EQU 0x000F0000
Pin_Night__0__HSIOM_SHIFT EQU 16
Pin_Night__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
Pin_Night__0__INTR EQU CYREG_GPIO_PRT3_INTR
Pin_Night__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
Pin_Night__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
Pin_Night__0__MASK EQU 0x10
Pin_Night__0__PC EQU CYREG_GPIO_PRT3_PC
Pin_Night__0__PC2 EQU CYREG_GPIO_PRT3_PC2
Pin_Night__0__PORT EQU 3
Pin_Night__0__PS EQU CYREG_GPIO_PRT3_PS
Pin_Night__0__SHIFT EQU 4
Pin_Night__DR EQU CYREG_GPIO_PRT3_DR
Pin_Night__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
Pin_Night__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
Pin_Night__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
Pin_Night__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
Pin_Night__INTR EQU CYREG_GPIO_PRT3_INTR
Pin_Night__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
Pin_Night__INTSTAT EQU CYREG_GPIO_PRT3_INTR
Pin_Night__MASK EQU 0x10
Pin_Night__PC EQU CYREG_GPIO_PRT3_PC
Pin_Night__PC2 EQU CYREG_GPIO_PRT3_PC2
Pin_Night__PORT EQU 3
Pin_Night__PS EQU CYREG_GPIO_PRT3_PS
Pin_Night__SHIFT EQU 4

; RELAY_ST1
RELAY_ST1__0__DR EQU CYREG_GPIO_PRT2_DR
RELAY_ST1__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_ST1__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_ST1__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_ST1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
RELAY_ST1__0__HSIOM_MASK EQU 0x0000F000
RELAY_ST1__0__HSIOM_SHIFT EQU 12
RELAY_ST1__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST1__0__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_ST1__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST1__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_ST1__0__MASK EQU 0x08
RELAY_ST1__0__PC EQU CYREG_GPIO_PRT2_PC
RELAY_ST1__0__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_ST1__0__PORT EQU 2
RELAY_ST1__0__PS EQU CYREG_GPIO_PRT2_PS
RELAY_ST1__0__SHIFT EQU 3
RELAY_ST1__DR EQU CYREG_GPIO_PRT2_DR
RELAY_ST1__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_ST1__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_ST1__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_ST1__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST1__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_ST1__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST1__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_ST1__MASK EQU 0x08
RELAY_ST1__PC EQU CYREG_GPIO_PRT2_PC
RELAY_ST1__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_ST1__PORT EQU 2
RELAY_ST1__PS EQU CYREG_GPIO_PRT2_PS
RELAY_ST1__SHIFT EQU 3

; RELAY_ST2
RELAY_ST2__0__DR EQU CYREG_GPIO_PRT3_DR
RELAY_ST2__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
RELAY_ST2__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
RELAY_ST2__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
RELAY_ST2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
RELAY_ST2__0__HSIOM_MASK EQU 0x000000F0
RELAY_ST2__0__HSIOM_SHIFT EQU 4
RELAY_ST2__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_ST2__0__INTR EQU CYREG_GPIO_PRT3_INTR
RELAY_ST2__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_ST2__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
RELAY_ST2__0__MASK EQU 0x02
RELAY_ST2__0__PC EQU CYREG_GPIO_PRT3_PC
RELAY_ST2__0__PC2 EQU CYREG_GPIO_PRT3_PC2
RELAY_ST2__0__PORT EQU 3
RELAY_ST2__0__PS EQU CYREG_GPIO_PRT3_PS
RELAY_ST2__0__SHIFT EQU 1
RELAY_ST2__DR EQU CYREG_GPIO_PRT3_DR
RELAY_ST2__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
RELAY_ST2__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
RELAY_ST2__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
RELAY_ST2__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_ST2__INTR EQU CYREG_GPIO_PRT3_INTR
RELAY_ST2__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_ST2__INTSTAT EQU CYREG_GPIO_PRT3_INTR
RELAY_ST2__MASK EQU 0x02
RELAY_ST2__PC EQU CYREG_GPIO_PRT3_PC
RELAY_ST2__PC2 EQU CYREG_GPIO_PRT3_PC2
RELAY_ST2__PORT EQU 3
RELAY_ST2__PS EQU CYREG_GPIO_PRT3_PS
RELAY_ST2__SHIFT EQU 1

; RELAY_ST3
RELAY_ST3__0__DR EQU CYREG_GPIO_PRT2_DR
RELAY_ST3__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_ST3__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_ST3__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_ST3__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
RELAY_ST3__0__HSIOM_MASK EQU 0xF0000000
RELAY_ST3__0__HSIOM_SHIFT EQU 28
RELAY_ST3__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST3__0__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_ST3__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST3__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_ST3__0__MASK EQU 0x80
RELAY_ST3__0__PC EQU CYREG_GPIO_PRT2_PC
RELAY_ST3__0__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_ST3__0__PORT EQU 2
RELAY_ST3__0__PS EQU CYREG_GPIO_PRT2_PS
RELAY_ST3__0__SHIFT EQU 7
RELAY_ST3__DR EQU CYREG_GPIO_PRT2_DR
RELAY_ST3__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_ST3__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_ST3__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_ST3__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST3__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_ST3__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_ST3__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_ST3__MASK EQU 0x80
RELAY_ST3__PC EQU CYREG_GPIO_PRT2_PC
RELAY_ST3__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_ST3__PORT EQU 2
RELAY_ST3__PS EQU CYREG_GPIO_PRT2_PS
RELAY_ST3__SHIFT EQU 7

; RELAY_SW1
RELAY_SW1__0__DR EQU CYREG_GPIO_PRT3_DR
RELAY_SW1__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
RELAY_SW1__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
RELAY_SW1__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
RELAY_SW1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
RELAY_SW1__0__HSIOM_MASK EQU 0x0000000F
RELAY_SW1__0__HSIOM_SHIFT EQU 0
RELAY_SW1__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_SW1__0__INTR EQU CYREG_GPIO_PRT3_INTR
RELAY_SW1__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_SW1__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
RELAY_SW1__0__MASK EQU 0x01
RELAY_SW1__0__PC EQU CYREG_GPIO_PRT3_PC
RELAY_SW1__0__PC2 EQU CYREG_GPIO_PRT3_PC2
RELAY_SW1__0__PORT EQU 3
RELAY_SW1__0__PS EQU CYREG_GPIO_PRT3_PS
RELAY_SW1__0__SHIFT EQU 0
RELAY_SW1__DR EQU CYREG_GPIO_PRT3_DR
RELAY_SW1__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
RELAY_SW1__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
RELAY_SW1__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
RELAY_SW1__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_SW1__INTR EQU CYREG_GPIO_PRT3_INTR
RELAY_SW1__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
RELAY_SW1__INTSTAT EQU CYREG_GPIO_PRT3_INTR
RELAY_SW1__MASK EQU 0x01
RELAY_SW1__PC EQU CYREG_GPIO_PRT3_PC
RELAY_SW1__PC2 EQU CYREG_GPIO_PRT3_PC2
RELAY_SW1__PORT EQU 3
RELAY_SW1__PS EQU CYREG_GPIO_PRT3_PS
RELAY_SW1__SHIFT EQU 0

; RELAY_SW2
RELAY_SW2__0__DR EQU CYREG_GPIO_PRT2_DR
RELAY_SW2__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_SW2__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_SW2__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_SW2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
RELAY_SW2__0__HSIOM_MASK EQU 0x000000F0
RELAY_SW2__0__HSIOM_SHIFT EQU 4
RELAY_SW2__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW2__0__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_SW2__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW2__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_SW2__0__MASK EQU 0x02
RELAY_SW2__0__PC EQU CYREG_GPIO_PRT2_PC
RELAY_SW2__0__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_SW2__0__PORT EQU 2
RELAY_SW2__0__PS EQU CYREG_GPIO_PRT2_PS
RELAY_SW2__0__SHIFT EQU 1
RELAY_SW2__DR EQU CYREG_GPIO_PRT2_DR
RELAY_SW2__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_SW2__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_SW2__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_SW2__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW2__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_SW2__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW2__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_SW2__MASK EQU 0x02
RELAY_SW2__PC EQU CYREG_GPIO_PRT2_PC
RELAY_SW2__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_SW2__PORT EQU 2
RELAY_SW2__PS EQU CYREG_GPIO_PRT2_PS
RELAY_SW2__SHIFT EQU 1

; RELAY_SW3
RELAY_SW3__0__DR EQU CYREG_GPIO_PRT2_DR
RELAY_SW3__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_SW3__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_SW3__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_SW3__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
RELAY_SW3__0__HSIOM_MASK EQU 0x00000F00
RELAY_SW3__0__HSIOM_SHIFT EQU 8
RELAY_SW3__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW3__0__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_SW3__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW3__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_SW3__0__MASK EQU 0x04
RELAY_SW3__0__PC EQU CYREG_GPIO_PRT2_PC
RELAY_SW3__0__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_SW3__0__PORT EQU 2
RELAY_SW3__0__PS EQU CYREG_GPIO_PRT2_PS
RELAY_SW3__0__SHIFT EQU 2
RELAY_SW3__DR EQU CYREG_GPIO_PRT2_DR
RELAY_SW3__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
RELAY_SW3__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
RELAY_SW3__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
RELAY_SW3__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW3__INTR EQU CYREG_GPIO_PRT2_INTR
RELAY_SW3__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
RELAY_SW3__INTSTAT EQU CYREG_GPIO_PRT2_INTR
RELAY_SW3__MASK EQU 0x04
RELAY_SW3__PC EQU CYREG_GPIO_PRT2_PC
RELAY_SW3__PC2 EQU CYREG_GPIO_PRT2_PC2
RELAY_SW3__PORT EQU 2
RELAY_SW3__PS EQU CYREG_GPIO_PRT2_PS
RELAY_SW3__SHIFT EQU 2

; Clock_Beep
Clock_Beep__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL3
Clock_Beep__DIV_ID EQU 0x00000045
Clock_Beep__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL5
Clock_Beep__PA_DIV_ID EQU 0x000000FF

; Clock_Local
Clock_Local__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL7
Clock_Local__DIV_ID EQU 0x00000041
Clock_Local__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1
Clock_Local__PA_DIV_ID EQU 0x000000FF

; Clock_Night
Clock_Night__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL5
Clock_Night__DIV_ID EQU 0x00000042
Clock_Night__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL2
Clock_Night__PA_DIV_ID EQU 0x000000FF

; PWM_Distict_cy_m0s8_tcpwm_1
PWM_Distict_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT1_CC
PWM_Distict_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT1_CC_BUFF
PWM_Distict_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT1_COUNTER
PWM_Distict_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT1_CTRL
PWM_Distict_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT1_INTR
PWM_Distict_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT1_INTR_MASK
PWM_Distict_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT1_INTR_MASKED
PWM_Distict_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT1_INTR_SET
PWM_Distict_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT1_PERIOD
PWM_Distict_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT1_PERIOD_BUFF
PWM_Distict_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT1_STATUS
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x02
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 1
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x200
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 9
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x2000000
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 25
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x20000
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 17
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x02
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 1
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x02
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 1
PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 1
PWM_Distict_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT1_TR_CTRL0
PWM_Distict_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT1_TR_CTRL1
PWM_Distict_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT1_TR_CTRL2

; Pin_Distict
Pin_Distict__0__DR EQU CYREG_GPIO_PRT2_DR
Pin_Distict__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_Distict__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_Distict__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_Distict__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
Pin_Distict__0__HSIOM_MASK EQU 0x0F000000
Pin_Distict__0__HSIOM_SHIFT EQU 24
Pin_Distict__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Distict__0__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_Distict__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Distict__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_Distict__0__MASK EQU 0x40
Pin_Distict__0__PC EQU CYREG_GPIO_PRT2_PC
Pin_Distict__0__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_Distict__0__PORT EQU 2
Pin_Distict__0__PS EQU CYREG_GPIO_PRT2_PS
Pin_Distict__0__SHIFT EQU 6
Pin_Distict__DR EQU CYREG_GPIO_PRT2_DR
Pin_Distict__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
Pin_Distict__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
Pin_Distict__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
Pin_Distict__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Distict__INTR EQU CYREG_GPIO_PRT2_INTR
Pin_Distict__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
Pin_Distict__INTSTAT EQU CYREG_GPIO_PRT2_INTR
Pin_Distict__MASK EQU 0x40
Pin_Distict__PC EQU CYREG_GPIO_PRT2_PC
Pin_Distict__PC2 EQU CYREG_GPIO_PRT2_PC2
Pin_Distict__PORT EQU 2
Pin_Distict__PS EQU CYREG_GPIO_PRT2_PS
Pin_Distict__SHIFT EQU 6

; Clock_Distict
Clock_Distict__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL4
Clock_Distict__DIV_ID EQU 0x00000043
Clock_Distict__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL3
Clock_Distict__PA_DIV_ID EQU 0x000000FF

; Miscellaneous
CYDEV_BCLK__HFCLK__HZ EQU 24000000
CYDEV_BCLK__HFCLK__KHZ EQU 24000
CYDEV_BCLK__HFCLK__MHZ EQU 24
CYDEV_BCLK__SYSCLK__HZ EQU 24000000
CYDEV_BCLK__SYSCLK__KHZ EQU 24000
CYDEV_BCLK__SYSCLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 19
CYDEV_CHIP_DIE_PSOC4A EQU 11
CYDEV_CHIP_DIE_PSOC5LP EQU 18
CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x190F11A9
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 11
CYDEV_CHIP_MEMBER_4C EQU 16
CYDEV_CHIP_MEMBER_4D EQU 7
CYDEV_CHIP_MEMBER_4E EQU 4
CYDEV_CHIP_MEMBER_4F EQU 12
CYDEV_CHIP_MEMBER_4G EQU 2
CYDEV_CHIP_MEMBER_4H EQU 10
CYDEV_CHIP_MEMBER_4I EQU 15
CYDEV_CHIP_MEMBER_4J EQU 8
CYDEV_CHIP_MEMBER_4K EQU 9
CYDEV_CHIP_MEMBER_4L EQU 14
CYDEV_CHIP_MEMBER_4M EQU 13
CYDEV_CHIP_MEMBER_4N EQU 6
CYDEV_CHIP_MEMBER_4O EQU 5
CYDEV_CHIP_MEMBER_4U EQU 3
CYDEV_CHIP_MEMBER_5A EQU 18
CYDEV_CHIP_MEMBER_5B EQU 17
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4J
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4J_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DFT_SELECT_CLK0 EQU 8
CYDEV_DFT_SELECT_CLK1 EQU 9
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0200
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD_MV EQU 3300
CYDEV_WDT_GENERATE_ISR EQU 0
CYIPBLOCK_m0s8cpussv3_VERSION EQU 1
CYIPBLOCK_m0s8csdv2_VERSION EQU 1
CYIPBLOCK_m0s8ioss_VERSION EQU 1
CYIPBLOCK_m0s8lcd_VERSION EQU 2
CYIPBLOCK_m0s8lpcomp_VERSION EQU 2
CYIPBLOCK_m0s8peri_VERSION EQU 1
CYIPBLOCK_m0s8scb_VERSION EQU 2
CYIPBLOCK_m0s8tcpwm_VERSION EQU 2
CYIPBLOCK_m0s8wco_VERSION EQU 1
CYIPBLOCK_s8srsslt_VERSION EQU 1
CYDEV_BOOTLOADER_ENABLE EQU 0
    ENDIF
    END
